Some liquid crystal panels are different in structure from normal liquid crystal panels, and are configured such that a memory circuit is included in each pixel (hereinafter referred to as a pixel memory). In order for a still image to be displayed on such a liquid crystal panel, it is only necessary that data of the still image be retained in the pixel memory. This makes it unnecessary to continue sending (scanning) the image. Therefore, a high-speed clock signal, which has been required for continuing to send the image, becomes unnecessary except when the image is rewritten (that is, unnecessary while a still image is being displayed).
FIG. 6 is a block diagram illustrating a conventional liquid crystal display device 101. The liquid crystal display device 101 includes (i) a liquid crystal panel 102 in which a pixel memory is included in each pixel and (ii) a liquid crystal panel driving circuit 103. The liquid crystal panel 102 includes a gate driver 109.
[Liquid Crystal Panel Driving Circuit 103]
The liquid crystal panel driving circuit 103 includes an MPU (Micro-Processing Unit) 104 and an LCD (liquid crystal display) driver 105 (LCD controller).
The LCD driver 105 includes an MPU interface 106, an image storing RAM (Random Access Memory) 107a, a source driver 107b, a high-speed oscillation circuit 108, a frequency dividing section 110, a polarity-reversed signal output section 111, and a power supply circuit 112 (booster circuit).
In FIG. 6, the power supply circuit 112 and the polarity-reversed signal output section 111 are required to operate constantly by a low-speed clock signal L-CLK (described later). The power supply circuit 112 supplies a power supply voltage V1cd and electric power to the liquid crystal panel 102. Further, the power supply circuit 112 supplies an internal circuit power supply voltage to an internal circuit of the liquid crystal panel driving circuit 103, which is an IC (Integrated Circuit). In addition, the power supply circuit 112 supplies a power supply voltage V1 to the polarity-reversed signal output section 111 and supplies a power supply voltage V2 to the source driver 7b. 
The polarity-reversed signal output section 111 supplies signals VA and VB to the liquid crystal panel 102, and supplies a signal Vcom (described later) to a common electrode COM (not illustrated) of the liquid crystal panel 102.
According to the liquid crystal panel driving circuit 103, image data is supplied from the MPU 104 to the image storing RAM 107a via the MPU interface 106, and is written to the image storing RAM 107a. In this way, an image to be displayed on the liquid crystal panel 102 is supplied. The image data is written in accordance with a write pulse (pulse signal) supplied from the MPU 104, which write pulse serves as a clock signal (writing clock signal). Therefore, it is not necessary to provide an oscillation circuit exclusively for writing image data.
The high-speed oscillation circuit 108 supplies a high-speed clock signal H-CLK to the source driver 107b and to the frequency dividing section 110, and supplies a gate start pulse signal GSP and a high-speed clock signal H-CLK (gate clock signal GCK) to the gate driver 109. This causes image data to be supplied from the image storing RAM 107a to the liquid crystal panel 102 via the source driver 107b, and selection signals S11, •S12, • . . . • and S1n to be supplied from the gate driver 109 to a display region 102a of the liquid crystal panel 102. In this way, an image is displayed on the liquid crystal panel 102.
The image data written to the image storing RAM 107 is supplied via a bus between the image storing RAM 107 and the liquid crystal panel 102.
The frequency dividing section 110 divides the high-speed clock signal H-CLK supplied from the high-speed oscillation circuit 108 to generate a low-speed clock signal L-CLK. The low-speed clock signal L-CLK thus generated is supplied to the polarity-reversed signal output section 111 and the power supply circuit 112.
In the liquid crystal display device 101 shown in FIG. 6, in order for the pixels of the liquid crystal panel 102 to retain pixel values, it is necessary to reverse polarity of the signals Vcom that is constantly supplied to the common electrode COM and polarities of the signals VA and VB.
Note here that the low-speed clock signal L-CLK, which is required for supplying the signals Vcom, VA, and VB, is slower (lower in frequency) than the high-speed clock signal H-CLK. As described earlier, the high-speed clock signal H-CLK is not necessary while a still image is being displayed. However, according to the liquid crystal display device 101 shown in FIG. 6, it is necessary to continue supplying the high-speed clock signal H-CLK in order to supply the low-speed clock signal L-CLK, even while a still image is being displayed. This leads to excess power consumption.
Under this circumstances, Patent Literatures 1 and 2 each disclose an invention for preventing excess power consumption while pixels are not being rewritten. The Patent Literature 1 discloses a liquid crystal driving device which includes two oscillation circuits (specifically, a high-speed oscillation circuit and a low-speed oscillation circuit) and causes the high-speed oscillation circuit to operate only when an image is rewritten.
FIG. 7 is a view corresponding to FIG. 1 of Patent Literature 1. The liquid crystal driving device shown in FIG. 7 includes an MPU interface 210, a bus holder 220, a VRAM control 230, and a timing control 240. The liquid crystal driving device further includes a high-frequency oscillation circuit 250 (a high-speed oscillation circuit) used only when an image is rewritten and a low-frequency oscillation circuit 270 (a low-speed oscillation circuit).
On the other hand, Patent Literature 2 discloses a drive circuit in which a power supply circuit operates only when an image is rewritten and does not operate at other times. FIG. 8 is a view corresponding to FIG. 1 of the Patent Literature 2. The drive circuit shown in FIG. 8 includes a line driver 121, a column driver 131, an MPU interface section 141, a command decoder 142, a timing generator circuit 143, an oscillation circuit 144, a display data RAM 145, and an address control circuit 146. The drive circuit further includes a power supply circuit 155. The power supply circuit 155 operates only when an image is rewritten and does not operate at other times.